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74CBTLV3126
4-bit bus switch
Rev. 01 -- 5 January 2010 Product data sheet
1. General description
The 74CBTLV3126 provides a 4-bit high-speed bus switch with separate output enable inputs (1OE to 4OE). The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The switch is disabled (high-impedance OFF-state) when the output enable (nOE) input is LOW. To ensure the high-impedance OFF-state during power-up or power-down, nOE should be tied to the GND through a pull-down resistor. The minimum value of the resistor is determined by the current-sinking capability of the driver. Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 2.3 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
2. Features
Supply voltage range from 2.3 V to 3.6 V Standard '126'-type pinout High noise immunity Complies with JEDEC standard: JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM AEC-Q100-011 revision B exceeds 1000 V 5 switch connection between two ports Rail to rail switching on data I/O ports CMOS low power consumption Latch-up performance exceeds 250 mA per JESD78B Class I level A IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from -40 C to +85 C and -40 C to +125 C
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NXP Semiconductors
74CBTLV3126
4-bit bus switch
3. Ordering information
Table 1. Ordering information Package Temperature range Name 74CBTLV3126DS 74CBTLV3126PW 74CBTLV3126BQ -40 C to +125 C -40 C to +125 C -40 C to +125 C SSOP16[1] TSSOP14 Description plastic shrink small outline package; 16 leads; body width 3.9 mm; lead pitch 0.635 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm Version SOT519-1 SOT402-1 SOT762-1 Type number
DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm
[1]
Also known as QSOP16.
4. Functional diagram
1OE 1A 2OE 2A 3OE 3A 4OE 4A 4B
001aaj023
1B
2B
3B nA nB
nOE
001aal245
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Fig 1.
Logic symbol
Fig 2.
Logic diagram (one switch)
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Product data sheet
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4-bit bus switch
5. Pinning information
5.1 Pinning
74CBTLV3126
1OE 2 3 4 5 6 7 GND 3B 8 GND(1) 1
74CBTLV3126 74CBTLV3126
n.c. 1OE 1A 1B 2OE 2A 2B GND 1 2 3 4 5 6 7 8
001aal246
terminal 1 index area 16 VCC 15 4OE 14 4A 13 4B 12 3OE 11 3A 10 3B 9 n.c. 1OE 1A 1B 2OE 2A 2B GND 1 2 3 4 5 6 7
001aal247
14 VCC 13 4OE 12 4A 11 4B 10 3OE 9 3A
1A 14 VCC 13 4OE 12 4A 11 4B 10 3OE 9 8 3A 3B 2B 1B 2OE 2A
001aal248
Transparent top view
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.
Fig 3.
Pin configuration SOT519-1 (SSOP16)
Fig 4.
Pin configuration SOT402-1 (TSSOP14)
Fig 5.
Pin configuration SOT762-1 (DHVQFN14)
5.2 Pin description
Table 2. Symbol 1OE to 4OE 1A to 4A, 1B to 4B GND VCC n.c. Pin description Pin SOT402-1 and SOT762-1
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Description SOT519-1 2, 5, 12, 15 3, 6, 11, 14 4, 7, 10, 13 8 16 1, 9 output enable input A input/output B output/input ground (0 V) positive supply voltage not connected
1, 4, 10, 13 2, 5, 9, 12 3, 6, 8, 11 7 14 -
6. Functional description
Table 3. L H
[1] H = HIGH voltage level; L = LOW voltage level.
Function table[1] Function switch OFF-state ON-state
Output enable input OE
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Product data sheet
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4-bit bus switch
7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI VSW IIK ISK ISW ICC IGND Tstg Ptot
[1] [2] [3]
Parameter supply voltage input voltage switch voltage input clamping current switch clamping current switch current supply current ground current storage temperature total power dissipation
Conditions control inputs enable and disable mode VI < -0.5 V VI < -0.5 V or VI > VCC + 0.5 V VSW = 0 V to VCC
[1] [2]
Min -0.5 -0.5 -0.5 -50 -100 -65
Max +4.6 +4.6 VCC + 0.5 50 128 +100 +150 500
Unit V V V mA mA mA mA mA C mW
Tamb = -40 C to +125 C
[3]
-
The minimum input voltage rating may be exceeded if the input clamping current ratings are observed. The switch voltage ratings may be exceeded if switch clamping current ratings are observed For SSOP16 and TSSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C. For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.
8. Recommended operating conditions
Table 5. Symbol VCC VI Tamb t/V Recommended operating conditions Parameter supply voltage input voltage ambient temperature input transition rise and fall rate pin nOE; VCC = 2.3 V to 3.6 V control inputs enable and disable mode Conditions Min 2.3 0 0 -40 0 Max 3.6 3.6 VCC +125 200 Unit V V V C ns/V
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9. Static characteristics
Table 6. Static characteristics At recommended operating conditions voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL II IS(OFF) HIGH-level input voltage Conditions VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V Tamb = -40 C to +85 C Min 1.7 2.0 Typ[1] Max 0.7 0.9 1.0 1 Tamb = -40 C to +125 C Unit Min 1.7 2.0 Max 0.7 0.9 20 20 V V V V A A
LOW-level input VCC = 2.3 V to 2.7 V voltage VCC = 3.0 V to 3.6 V input leakage current pin nOE; VI = GND to VCC; VCC = 3.6 V
OFF-state VCC = 3.6 V; see Figure 6 leakage current
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Product data sheet
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4-bit bus switch
Table 6. Static characteristics ...continued At recommended operating conditions voltages are referenced to GND (ground = 0 V). Symbol Parameter IS(ON) IOFF ICC Conditions Tamb = -40 C to +85 C Min ON-state VCC = 3.6 V; see Figure 7 leakage current power-off VI or VO = 0 V to 3.6 V; leakage current VCC = 0 V supply current VI = GND or VCC; IO = 0 A; VSW = GND or VCC; VCC = 3.6 V pin nOE; VI = VCC - 0.6 V; VSW = GND or VCC; VCC = 3.6 V pin nOE; VCC = 3.3 V; VI = 0 V to 3.3 V VCC = 3.3 V; VI = 0 V to 3.3 V VCC = 3.3 V; VI = 0 V to 3.3 V
[2]
Tamb = -40 C to +125 C Unit Min Max 20 50 50 A A A
Typ[1] -
Max 1 10 10
-
ICC
additional supply current input capacitance OFF-state capacitance ON-state capacitance
-
-
300
-
2000
A
CI CS(OFF) CS(ON)
-
0.9 5.2 14.3
-
-
-
pF pF pF
[1] [2]
All typical values are measured at Tamb = 25 C. One input at 3 V, other inputs at VCC or GND.
9.1 Test circuits
VCC nOE
IS
VCC nOE A
VO VI IS
VIL
VIH
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VI IS
nB
nA GND
A
nA
nB GND
VO
001aal249
001aal250
VI = VCC or GND and VO = GND or VCC.
VI = VCC or GND and VO = open circuit.
Fig 6.
Test circuit for measuring OFF-state leakage current (one switch)
Fig 7.
Test circuit for measuring ON-state leakage current (one switch)
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Product data sheet
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74CBTLV3126
4-bit bus switch
9.2 ON resistance
Table 7. Resistance RON At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter RON Conditions
[2]
Tamb = -40 C to +85 C Min Typ[1] Max
Tamb = -40 C to +125 C Min Max
Unit
ON resistance VCC = 2.3 V to 2.7 V; see Figure 9 to Figure 11 ISW = 64 mA; VI = 0 V ISW = 24 mA; VI = 0 V ISW = 15 mA; VI = 1.7 V VCC = 3.0 V to 3.6 V; see Figure 12 to Figure 14 ISW = 64 mA; VI = 0 V ISW = 24 mA; VI = 0 V ISW = 15 mA; VI = 2.4 V
-
4.2 4.2 8.4
8.0 8.0 40.0
-
15.0 15.0 60.0

-
4.0 4.0 6.2
7.0 7.0 15.0
-
11.0 11.0 25.5

[1] [2]
Typical values are measured at Tamb = 25 C and nominal VCC. Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals.
9.3 ON resistance test circuit and graphs
11 RON () 9
VSW 001aai109
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V 7 VCC nOE 5 nA
VI (1) (2) (3)
VIH
nB GND
ISW
(4)
3 0
001aal251
0.5
1.0
1.5
2.0 VI (V)
2.5
RON = VSW / ISW.
(1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = -40 C.
Fig 8.
Test circuit for measuring ON resistance (one switch)
Fig 9.
ON resistance as a function of input voltage; VCC = 2.5 V; ISW = 15 mA
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11 RON () 9
001aai110
11 RON () 9
001aai111
7
7
(1)
(1)
5
(2) (3) (4)
5
(2) (3) (4)
3 0 0.5 1.0 1.5 2.0 VI (V) 2.5
3 0 0.5 1.0 1.5 2.0 VI (V) 2.5
(1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = -40 C.
(1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = -40 C.
Fig 10. ON resistance as a function of input voltage; VCC = 2.5 V; ISW = 24 mA
Fig 11. ON resistance as a function of input voltage; VCC = 2.5 V; ISW = 64 mA
8 RON () 6
001aai105
8 RON () 6
(1) (2)
001aai106
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(1) (2)
4
(3) (4)
4
(3) (4)
2 0 1 2 3 VI (V) 4
2 0 1 2 3 VI (V) 4
(1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = -40 C.
(1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = -40 C.
Fig 12. ON resistance as a function of input voltage; VCC = 3.3 V; ISW = 15 mA
Fig 13. ON resistance as a function of input voltage; VCC = 3.3 V; ISW = 24 mA
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Product data sheet
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74CBTLV3126
4-bit bus switch
7.5 RON () 6.5
001aai107
5.5
(1) (2)
4.5
(3)
3.5
(4)
2.5 0 1 2 3 VI (V) 4
(1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = -40 C.
Fig 14. ON resistance as a function of input voltage; VCC = 3.3 V; ISW = 64 mA
10. Dynamic characteristics
Table 8. Dynamic characteristics GND = 0 V; for test circuit see Figure 17 Symbol Parameter
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Conditions nA to nB or nB to nA; see Figure 15 VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V
[2][3]
Tamb = -40 C to +85 C Tamb = -40 C to +125 C Unit Min Typ[1] Max Min Max
[4]
-
0.13 0.20
-
0.20 0.31
ns ns
ten
enable time
nOE to nA or nB; see Figure 16 VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V
1.0 1.0
[5]
2.5 2.2
4.5 4.2
1.0 1.0
6.0 6.0
ns ns
tdis
disable time
nOE to nA or nB; see Figure 16 VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V
1.0 1.0
2.6 3.4
4.7 4.8
1.0 1.0
6.5 6.5
ns ns
[1] [2] [3] [4] [5]
All typical values are measured at Tamb = 25 C and at nominal VCC. The propagation delay is the calculated RC time constant of the maximum on-state resistance of the switch and the load capacitance, when driven by an ideal voltage source (zero output impedance). tpd is the same as tPLH and tPHL. ten is the same as tPZH and tPZL. tdis is the same as tPHZ and tPLZ.
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11. Waveforms
VI input 0V tPHL VOH output VOL VM VM
001aai367
VM
VM
tPLH
Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 15. The data input (nA or nB) to output (nB or nA) propagation delays Table 9. VCC 2.3 V to 2.7 V 3.0 V to 3.6 V Measurement points Input VM 0.5VCC 0.5VCC VI VCC VCC tr = tf 2.0 ns 2.0 ns Output VM 0.5VCC 0.5VCC VX VOL + 0.15 V VOL + 0.3 V VY VOH - 0.15 V VOH - 0.3 V
Supply voltage
VI nOE input GND tPLZ VCC output LOW-to-OFF OFF-to-LOW tPZL VM
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VM VOL tPHZ VOH VX tPZH VY VM GND switch enabled switch disabled switch enabled
001aal252
output HIGH-to-OFF OFF-to-HIGH
Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 16. Enable and disable times
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Product data sheet
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VI negative pulse 0V
tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW
VEXT VCC VI VO
RL
VM
VI positive pulse 0V
VM
G
RT
DUT
CL RL
001aae331
Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times.
Fig 17. Test circuit for measuring switching times Table 10. VCC 2.3 V to 2.7 V 3.0 V to 3.6 V Test data Load CL 30 pF 50 pF RL 500 500 VEXT tPLH, tPHL open open tPZH, tPHZ GND GND tPZL, tPLZ 2VCC 2VCC
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12. Package outline
SSOP16: plastic shrink small outline package; 16 leads; body width 3.9 mm; lead pitch 0.635 mm SOT519-1
D
E
A
X
c y HE vM A
Z
16 9
A2 A1 (A 3) Lp L
1 8
A
detail X wM
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e
bp
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.73 A1 0.25 0.10 A2 1.55 1.40 A3 0.25 bp 0.31 0.20 c 0.25 0.18 D (1) 5.0 4.8 E (1) 4.0 3.8 e 0.635 HE 6.2 5.8 L 1 Lp 0.89 0.41 v 0.2 w 0.18 y 0.09 Z (1) 0.18 0.05 8 o 0
o
Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT519-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION
ISSUE DATE 99-05-04 03-02-18
Fig 18. Package outline SOT519-1 (SSOP16)
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TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c y HE vMA
Z
14
8
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
7
wM detail X
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0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18
Fig 19. Package outline SOT402-1 (TSSOP14)
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Product data sheet
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74CBTLV3126
4-bit bus switch
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm
D
B
A
A A1 E c
terminal 1 index area
detail X
terminal 1 index area e 2 L
e1 b 6 vMCAB wM C y1 C
C y
1 Eh
7 e
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14
8
13 Dh 0
9 X 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.1 2.9 Dh 1.65 1.35 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT762-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27
Fig 20. Package outline SOT762-1 (DHVQFN14)
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Product data sheet
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13. Abbreviations
Table 11. Acronym CDM CMOS DUT ESD HBM MM Abbreviations Description Charged Device Model Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model
14. Revision history
Table 12. Revision history Release date 20100105 Data sheet status Product data sheet Change notice Supersedes Document ID 74CBTLV3126_1
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Product data sheet
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15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
15.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such www..com information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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4-bit bus switch
17. Contents
1 2 3 4 5 5.1 5.2 6 7 8 9 9.1 9.2 9.3 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance test circuit and graphs. . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 5 January 2010 Document identifier: 74CBTLV3126_1

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